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HYS 64V16302GU SDRAM-Modules
3.3 V 16M x 64-Bit, 128MByte SDRAM Module 168-pin Unbuffered DIMM Modules
* 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications using 256Mbit technology * PC100-222, PC133-333 and PC133-222 versions * One bank 16M x 64 organization * Optimized for byte-write non-parity * JEDEC standard Synchronous DRAMs (SDRAM) * Single 3.3 V ( 0.3 V) power supply * SDRAM Performance: -7/ -7.5 -8 PC133 PC100 100 MHz Unit * Programmed Latencies: Product Speed -7 -7.5 -8 CL
tRCD
2 3 2
tRP
2 3 2
PC133 2 PC133 3 PC100 2
* Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * Decoupling capacitors mounted on substrate * All inputs and outputs are LVTTL compatible * Serial Presence Detect with E2PROM * Utilizes 16M x 16 (256Mbit SDRAMs in TSOPII-54 packages with 8096 refresh cycles every 64 ms * 133.35 mm x 29.21 mm x 3.00 mm card size with gold contact pads (JEDEC MO-161)
fCK Clock
Frequency (max.)
133
tAC Clock Access 5.4
Time
6
ns
Description The HYS 64V16302 is an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM) which is organized as 16M x 64 in an one bank high speed memory arrays designed with 256 Mbit Synchronous DRAMs for non-parity applications. The DIMMs use -7 speed sorted 16M x 16 organised 256Mbit SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, 7.5 for PC133-333 and -8 parts for the standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL's module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint. Important Notice: This module, which is based on 256MBit device technology can only be used in applications, where the 256Mbit addressing is supported.
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Ordering Information Type HYS 64V16302GU-7-D Code Package Description Module
Height
PC133-222-520 L-DIM-168-32 133 MHz CL=2 16M x 64 one bank SDRAM module 1.15" 1.15"
HYS 64V16302GU-7.5-C2 PC133-333-520 L-DIM-168-32 133 MHz CL=3 16M x 64 one bank SDRAM module HYS 64V16302GU-7.5-D HYS 64V16302GU-8-C2 PC100-222-620 L-DIM-168-32 100 MHz CL=2 16M x 64 one bank SDRAM module
Note: All part numbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS64V16302GU-8-C2, indicating Rev.C2 dies are used for SDRAM components. Pin Definitions and Functions A0 - A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7 RAS CAS WE CKE0 Address Inputs Bank Select Data Input/Output Check Bits (x72 organization only) Row Address Strobe Column Address Strobe Read/Write Input Clock Enable CLK0 - CLK3 CS0, CS2 Clock Input Chip Select Power (+ 3.3 V) Ground Clock for Presence Detect Serial Data Out for Pres. Detect No Connection
DQMB0 - DQMB7 Data Mask
VDD VSS
SCL SDA N.C./DU
Address Format Part Number 16Mx64 Rows Columns Bank Select 9 2 Refresh 8k Period 64 ms Interval 7,8 s
HYS64V16302GU 13
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Pin Configuration PIN#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Symbol
VSS
DQ0 DQ1 DQ2 DQ3
PIN#
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Symbol
VSS
DU CS2 DQMB2 DQMB3 DU
PIN#
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
Symbol
VSS
DQ32 DQ33 DQ34 DQ35
PIN#
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol
VSS
CKE0 N.C. DQMB6 DQMB7 N.C.
VDD
DQ4 DQ5 DQ6 DQ7 DQ8
VDD
DQ36 DQ37 DQ38 DQ39 DQ40
VDD
N.C. N.C. N.C. N.C.
VDD
N.C. N.C. CB6 CB7
VSS
DQ9 DQ10 DQ11 DQ12 DQ13
VSS
DQ16 DQ17 DQ18 DQ19
VSS
DQ41 DQ42 DQ43 DQ44 DQ45
VSS
DQ48 DQ49 DQ50 DQ51
VDD
DQ20 N.C. DU N.C.
VDD
DQ52 N.C. DU N.C.
VDD
DQ14 DQ15 N.C. N.C.
VDD
DQ46 DQ47 N.C. N.C.
VSS
DQ21 DQ22 DQ23
VSS
DQ53 DQ54 DQ55
VSS
N.C. N.C.
VSS
N.C. N.C.
VDD
WE DQMB0 DQMB1 CS0 DU
VSS
DQ24 DQ25 DQ26 DQ27
VDD
CAS DQMB4 DQMB5 N.C. RAS
VSS
DQ56 DQ57 DQ58 DQ59
VDD
DQ28 DQ29 DQ30 DQ31
VDD
DQ60 DQ61 DQ62 DQ63
VSS
A0 A2 A4 A6 A8 A10 BA1
VSS
A1 A3 A5 A7 A9 BA0 A11
VSS
CLK2 N.C. WP SDA SCL
VSS
CLK3 N.C. SA0 SA1 SA2
VDD VDD
CLK0
VDD
CLK1 A12
VDD
VDD
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Functional Block Diagrams
CS0, CLK0 CS, CLK LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 CS, CLK LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1
DQMB4 DQ32-DQ39 DQMB0 DQ0-DQ7
DQMB5 DQ40-DQ47 DQMB1 DQ8-DQ15
CS2, CLK2 CS, CLK LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 D0-D3 D0-D3 CS, CLK LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 E PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP 47 k
2
DQMB6 DQ48-DQ55 DQMB2 DQ16-DQ23
DQMB7 DQ56-DQ63 DQMB3 DQ24-DQ31
A0-A12, BA0, BA1
V CC C V SS
RAS, CAS, WE CKE0 CLK1, CLK3
D0-D3 D0-D3 D0-D3
Clock Wiring 8 M x 64
10 pF Notes: 1) All resistors are 10 Ohm except otherwise noted
CLK0 CLK1 CLK2 CLK3
2 SDRAM + 3.3 pF Termination 2 SDRAM + 3.3 pF Termination
BL03 7.8.00
Block Diagram: 16M x 64 One Bank SDRAM DIMM Modules (HYS 64V16302GU)
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Absolute Maximum Ratings
Parameter Symbol min. Input / Output voltage relative to VSS Power supply voltage on VDD Storage temperature range Power dissipation Data out current (short circuit) VIN, VOUT VDD, T STG PD IOS - 1.0 - 1.0 -55 - - Limit Values max. 4.6 4.6 +150 4 50 V V
o
Unit
C
W mA
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V Parameter Input High Voltage Input Low Voltage Output High Voltage (I OUT = - 4.0 mA) Output Low Voltage (IOUT = 4.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output Leakage Current (DQ is disabled, 0 V < V OUT < V DD) Capacitance Symbol min. Limit Values max. 2.0 - 0.5 2.4 - - 10 - 10 Unit V V V V
VIH VIL VOH VOL II(L) IO(L)
VDD + 0.3
0.8 - 0.4 10 10
A A
TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz
Parameter Input Capacitance (A0 - A12, RAS, CAS, WE) Input Capacitance (CS0 ,CS2) Input Capacitance (CLK0 - CLK3) Input Capacitance (CKE0) Input Capacitance (DQMB0 - DQMB7) Input /Output Capacitance (DQ0 - DQ63, CB0 - CB7) Input Capacitance (SCL, SA0-2) Input /Output Capacitance INFINEON Technologies 5 Symbol Limit Values max. 35 25 35 30 13 10 8 10 Unit pF pF pF pF pF pF pF pF 9.01
CI1 CI2 CICL CI3 CI4 CIO CSC CSD
HYS 64V16302GU SDRAM-Modules
Operating Currents per SDRAM component TA = 0 to 70 C, VDD = 3.3 V 0.3 V Parameter Operating current tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge standby current in Power Down Mode CS = V IH (MIN.), CKE V IL(MAX.) Precharge stand-by current in Non Power Down Mode CS = V IH (MIN.), CKE V IH(MIN.) No operating current tCK = min., CS = VIH (MIN.), active state (max. 4 banks) Burst Operating Current tCK = min Read command cycling Auto Refresh Current tCK = min Auto Refresh command cycling Self Refresh Current Self Refresh Mode CKE = 0.2 V Test Condition Symbol -7.5 - -8 max. 170 Unit Note mA
1)
ICC1
230
tCK = min
ICC2P
2
2
mA
1)
tCK = min
ICC2N
40
30
mA
1)
CKE VIH(MIN.) CKE VIL(MAX.) -
ICC3N ICC3P ICC4
50 10 170
45 10 120
mA mA mA
1) 1)
1, 2)
-
ICC5
150
100
mA
1)
ICC6
3
3
mA
1)
1. All values are shown per one SDRAM component. 2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency for-7 & -7.5 and at 100 MHz for -8 modules. Input signals are changed once during t CK, excepts for ICC6 and for stand-by currents when tCK = infinity. 3. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 are assumed and th data-out current is excluded.
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AC Characteristics 1), 2) TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -7 -7.5 PC133-222 PC133-333 -8 PC100-222
Unit Note
min. max min. max. min. max. Clock Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System Frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Setup and Hold Times Input Setup Time Input Hold Time Power Down Mode Entry Time Power Down Mode Exit Setup Time Mode Register Setup Time Transition Time (rise and fall) Common Parameters RAS to CAS Delay Precharge Time Active Command Period Cycle Time Bank to Bank Delay Time
tCK
7.5 7.5 - - 133 133 5.4 5.4 - - 7.5 10 - - - - 2.5 2.5 - - 133 100 5.4 6 - - 10 10 - - - - 3 3 - - 100 100 6 6 - - ns ns
-
fCK
- - MHz MHz
-
tAC
- - ns ns ns ns
3), 4)
tCH tCL
2.5 2.5
4) 4)
tCS tCH tSB tPDE tRSC tT
1.5 0.8 - 1 2 1
- - 1 - - -
1.5 0.8 - 1 2 1
- - 1 - - -
2 1 - 1 2 1
- - 1 - - -
ns ns CLK CLK CLK ns
5) 5) 6) 7)
-
tRCD tRP tRAS tRC tRRD
15 15 42 60 14 1
- - - - - -
20 20 45 67.5 15 1
- - - - -
20 20 70 16 1
- - - - -
ns ns ns ns
- - - - -
100k 50
100k ns
CAS to CAS Delay Time (same bank) tCCD
CLK -
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AC Characteristics (cont'd) 1), 2)
TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values -7 -7.5 PC133-222 PC133-333 -8 PC100-222
Unit Note
min. max min. max. min. max. Refresh Cycle Refresh Period (8192 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time Data Out to Low Impedance Data Out to High Impedance DQM Data Out Disable Latency Write Cycle Data Input to Precharge (write recovery) DQM Write Mask Latency
tREF tSREX
64 -
- 1
- 1
64 -
- 1
64 -
ms CLK
6) 8)
tOH tLZ tHZ tDQZ
3 0 3 -
- - 7 2
3 0 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns
2)
-
9)
CLK -
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK - CLK -
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Notes 1. All AC characteristics are shown for the SDRAM components. An initial pause of 100 s is required after power-up. Then a Precharge All Banks command must be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/ ns edge rate between 0.8 V and 2.0 V. 3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns must be added to this parameter. 4. Rated at 1.4 V. 5. If tT is longer than 1 ns, a time (tT - 1) ns must be added to this parameter. 6. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 7. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle. 8. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 9. This is referenced to the time at which the output achieved the open circuit condition, not to output voltage levels.
t CH CLOCK 1.4 V t CL t IH tT 2.4 V 0.4 V
t IS
INPUT tAC t LZ OUTPUT
1.4 V tAC t OH
I/O
1.4 V t HZ
IO.vsd
50 pF
Measurement conditions for tAC and tOH
Serial Presence Detect A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus).
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SPD-Table for 16M x 64 (128 MByte non-ECC) Modules HYS64V16302GU Byte# Description SPD Entry Value -7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 3 SDRAM Access Time at CL = 3 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-toBack Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time at CL = 2 SDRAM Access Time at CL = 2 SDRAM Cycle Time at CL = 1 SDRAM Access Time at CL = 1 Minimum Row Precharge Time Min. Row to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Hold Time SDRAM Data Input Setup Time 128 256 SDRAM 13 10 1 64 0 LVTTL 7.5 / 10 ns 5.4 / 6 ns non-ECC Self-Refresh, 7.8 s x16 na tCCD = 1 CLK 1, 2, 4 & 8 4 CL = 2 & 3 CS latency = 0 Write latency = 0 unbuffered VDD tol +/- 10% 7.5 / 10.0 ns 5.4 / 6.0 ns not supported not supported 15 / 20 ns 14 / 15 / 16 ns 15 / 20 ns 42 / 45 / 50 ns 256 MByte 1.5 / 2.0 ns 0.8 / 1.0 ns 1.5 / 2.0 ns 0.8 / 1.0 ns 10 Hex 16M x 64 -7.5 80 08 04 0D 09 01 40 00 01 75 54 00 82 10 00 01 0F 04 06 01 01 00 0E A0 60 FF FF 14 0F 14 2D 20 15 08 15 08
-8
75 54
A0 60
75 54 00 00 0F 0E 0F 2A 15 08 15 08
A0 60 FF FF 14 10 14 2D 20 10 20 10 9.01
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HYS 64V16302GU SDRAM-Modules
Byte# Description
SPD Entry Value
36-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-125 126 127 128+
Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Locaction Module Part Number Module Revision Code Module Manufacturing Code Module Serial Number Superset Information Frequency Specification 100 MHz Support Details Unused Storage Locations
- Revision 1.2 - -
Hex 16M x 64 -7 -7.5 -8 FF FF FF 12 12 12 DA 1D 7B C1 INFINEO(N)
- -
64 AF FF
64 AF FF
64 AF FF
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Package Outlines L-DIM-168-32 (JEDEC MO-161-BA) SDRAM DIMM Module Package
133.35 + 0.15
127.35
29.21 + 0.13
3 max.
4 3 1 3 1.27 10 11 6.35 42.18 91 x 1.27 = 115.57 3.125 66.68 85 94 2 95 124 125 168 40 41 6.35 84 1.27 + 0.1
17.78
3 min.
Detail of Contacts
0.25
1 1.27
Note: All tolerances according to JEDEC standard
2.55
L-DIM-168-32
Dimensions in mm
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Change List i
1.00 7.00
Initial Release, Preliminary Information Block Diagram changes to actual L-DIM-168-32 circuitry Clock waveform measurements on various PC133 platforms showed optimisation potential for the value of the added capacitor for each Clock Input. The 15 pF capacitor(INTEL PC100/PC133 modules specification) is not hte optimal solutio and has been changed to 3.3 pF 256M S14 based modules and -7 added SCR : Absolute Maximum Rating Table added
7-8-2000
25-07-2001 06-09-2001
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